In a semiconductor device which has a main circuit including a metal insulator semiconductor field effect transistor (MISFET) as a field-effect transistor, an addition circuit (add-on circuit) which is added to a main circuit is formed so as to be separate from the main circuit to achieve a main function of the semiconductor device in some cases. For example, as an example of the addition circuit, a memory that stores trimming information or others can be exemplified.
As such a memory that stores the trimming information, a non-volatile memory (NV memory) with a floating gate structure, which is suitable to be mixedly mounted with the field-effect transistor included in the main circuit, has been used. In addition, as a non-volatile memory whose memory cell size can be reduced, usage of a non-volatile memory having a metal oxide nitride oxide semiconductor (MONOS) structure has been studied.
Japanese Patent Application Laid-Open Publication No. 2007-281091 (Patent Document 1) discloses a technique of forming a gate electrode and a resistor body by depositing a conductor film made of, for example, polycrystalline silicon on the main surface of the semiconductor substrate, and then, etching the conductor film in a semiconductor device provided with a plurality of non-volatile memories on a main surface of a semiconductor substrate.
Japanese Patent Application Laid-Open Publication No. H11-297848 (Patent Document 2) discloses a technique of forming a polycrystalline gate electrode layer on the gate insulating film while changing grain sizes depending on the type of the transistor by collectively forming gate insulating films of a plurality of types of transistors on a surface of a semiconductor substrate by performing a deposition process once in a method of manufacturing a semiconductor device.